1. Field of the Invention
The present invention relates to a semiconductor memory device which can be operated stably within a wide power supply voltage range and, more specifically, to a semiconductor memory device used in a static random access memory for stabilizing the operation of the memory cells in accordance with variations in the power supply voltage.
2. Description of the Related Art
The structure of a conventional semiconductor memory (static random access memory) will now be described, with reference to FIG. 1.
The semiconductor memory shown in FIG. 1 comprises a bit line load 50 and a memory cell 60 both connected to bit lines BL3 and BL4, as disclosed in IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October, 1990, pp. 1057-1062. The bit line load 50 includes N-channel MOSFETs 51 and 52. A power supply voltage VCC is applied to one end of each of the current paths of the N-channel MOSFETS and a gate electrode thereof, the other ends of the current paths of the N-channel MOSFETs being connected to the bit lines BL3 and BL4, respectively. The memory cell 60 includes transfer transistors 61 and 62, N-channel MOSFETs 63 and 64, and resistors R5 and R6. A plurality of memory cells corresponding to the memory cell 60 are connected to the bit lines BL3 and BL4, though this is not shown in FIG. 1.
The respective gate electrodes of the transfer transistors 61 and 62 are connected to a word line W2, one end of the current path of the transfer transistor 61 is connected to the bit line BL3, and one end of the current path of the transfer transistor 62 is connected to the bit line BL4. The other end of the current path of the transfer transistor 61 is connected to the gate electrode of the N-channel MOSFET 64, and the other end of the current path of the transfer transistor 62 is connected to the gate electrode of the N-channel MOSFET 63.
One end of the current path of the N-channel MOSFET 63 is connected to one end of the resistor R5, the other end of the current path of the transfer transistor 61, and the gate electrode of the N-channel MOSFET 64. The other end of the current path of the N-channel MOSFET 63 is grounded. On the other hand, one end of the current path of the N-channel MOSFET 64 is connected to one end of the resistor R6, the other end of the current path of the transfer transistor 62, and the gate electrode of the N-channel MOSFET 63. The other end of the current path of the N-channel MOSFET 64 is grounded. A power supply voltage VCC is applied to the other end of each of the resistors R5 and R6.
An operation of the conventional semiconductor memory will now be described.
The word line W2 and bit lines BL3 and BL4 are selected to read data out of the memory cell 60. When the word line W2 is selected, a high-level signal is supplied to the gate electrodes of the transfer transistors 61 and 62, and the transfer transistor 61 is turned on, with the result that data is supplied to the bit lines BL3 and BL4 from the memory cell 60.
If, when data is read out from the memory cell 60, the power supply voltage VCC is higher than a reference voltage, the potentials at the bit lines BL3 and BL4 are increased, as is the potential (power supply voltage) at the gate electrode of the transfer transistor 61, thereby increasing the amount of cell current flowing through the memory cell 60. When the amount of cell current is large, the voltage drops, owing to a parasitic resistance in the memory cell 60, and the level of output data becomes unsteady, with the result that the operation of the memory cell 60 becomes unstable. If the ratio of driving force .beta. of the N-channel MOSFET 63 to driving force .beta. of the transfer transistor 61 is increased, the memory cell can be operated stably when the power supply voltage is high. However, this method has a drawback in that the memory cell increases in size as the driving force ratio increases. On the other hand, the amount of cell current can be suppressed by setting the impedance of the bit line load 50 in advance. However, this method has a drawback in that the amplitude of the voltage of the bit line is increased and the access speed is decreased.
In the conventional semiconductor memory described above, the bit line load is controlled by the product (WE.times.CS) of a WRITE signal (WE) and a chip selecting signal (CS), but is not controlled in accordance with a variation in the power supply voltage. A circuit for detecting such a variation is known from IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October, 1990, pp. 1082-1092. According to this journal, when the power supply voltage is higher than a predetermined threshold value, the output of the sensor becomes high. On the other hand, when the power supply voltage is lower than the threshold value, the output becomes low. However, in the conventional semiconductor memory, the impedance of the bit line load connected to the memory cell is not controlled based on a result obtained by detecting a variation in the power supply voltage in order that the memory cell can operate stably.